Electronic phase locked loops ("PLL"s) are well known and understood. Typically, a PLL comprises a variable frequency oscillator ("VFO") connected in feedback to a phase comparator. The phase comparator generates a signal proportionate to the phase difference between the fed-back output of the VFO and an external periodic reference signal. The frequency of the VFO is varied in direct response to the output of the phase comparator, to reduce this phase difference. Accordingly, the VFO maintains a desired average frequency locked to the frequency of the reference signal. However, the VFO will experience short term variations of phase and frequency as it "hunts" for the underlying frequency of the reference signal.
Typically, PLLs are used to synchronized the distinct clocks of two or more circuits, in frequency and phase. As well, PLLs may be used as frequency synthesizers, multipliers or dividers, and to demodulate phase or frequency modulated signals.
Many applications may require the generation of a digital signal representative of the phase difference generated by a phase comparator. Such a digital representation is desirable for generating a digital version of a demodulated signal, or for controlling a VFO. Moreover, a digital phase comparator is particularly useful in a digital phase locked loop, that locks two or more digital (ie. square wave) clocks.
Numerous phase comparators providing a digital output signal are known. One known comparator uses an analog to digital converter to convert a sensed analog phase difference into a digital signal. In order to achieve any significant accuracy, however, a phase comparator whose output is extremely well matched to the input of an associated analog to digital converter must be used. This typically requires a very linear phase comparator and a well matched voltage conversion factor from the comparator to the analog to digital converter.
Another comparator uses a locally generated digital reference clock having a fixed period. The clock is used to measure the time difference, in reference clock cycles, between transitions of the signals to be compared. A digital counter counts the number of elapsed reference clock periods between a transition of a first input signal, and a second input signal. As will be appreciated, the accuracy of such a comparator is directly related to the frequency of the reference clock. The measured phase difference will be quantized, in quanta proportional to the reference clock period. This naturally results in a quantization error that may be as great as a reference clock period. Obviously, improved accuracy and a reduced quantization error may be achieved by increasing the frequency of the reference clock. This solution, however, requires greater circuit complexity and tolerances to accommodate higher frequency signals. Moreover, the resulting signals require and dissipate more power.
Certain digital applications require extremely precise frequency synchronization and are therefore very susceptible to the errors associated with using PLLs incorporating either of the above phase comparators. Digital telephone switches in the public telephone network, for example, process bytes of pulse code modulated ("PCM") voice data sampled at a frequency of 8000 Hz. Switches are hierarchically arranged in strata, and switches in one stratum are synchronized to switches in the stratum, hierarchically above them. As the synchronization is hierarchical slight synchronization errors may propagate from switches in higher strata to switches in lower strata.
Using PLLs incorporating the above described comparators with their associated inaccuracies, may produce phase and frequency discrepancies in the network, resulting in errors.
The present invention attempts to overcome some of the disadvantages associated with known phase comparators and PLLs utilizing such comparators.